1. Field of the Invention
The present invention relates in general to a system for scrambling and descrambling distributed samples, and more particularly to a distributed sample scrambling system which generates samples of both scrambler and descrambler shift register generator sequences at sampling times of non-uniform intervals in order to scramble and descramble the scrambler input bitstream.
2. Description of the Prior Art
Conventionally. FSS (Frame Synchronous Scrambling) system and SSS (Self Synchronous Scrambling) system are known as a binary data scrambling and descrambling system. The SSS system has, however, a drawback of error multiplication effect, which is very critical in cell-based transmission, while it satisfies the required randomizing effect of data. Also, the FSS system has a disadvantage in that it can not satisfy the randomizing effect of data in case the frame size is not large enough even though such an error multiplication effect does not occur therein.
In an effort to solve the above problems occurring in both the FSS system and the SSS system, a distributed sample scrambling system (hereinafter, referred to simply as "the DSS system") was recently adopted for use in the cell-based physical layer of BISDN (Broadband Integrated Services Digital Network) by CCITT (International Telegraph and Telephone Consultative Committee), as described in CCITT Temporary Document 22, Appendix 2 to Annex 4, "Changes for the Distributed Sample Scrambler", June 1991.
The known DSS system is basically similar to the FSS system which scrambles and descrambles the digital bitstreams by adding the shift register generator (hereinafter, referred to simply as "the SRG") sequences to them. But in order to increase the randomizing effect of data, the DSS system is different from the FSS system in the method of synchronizing the state of the descramble SRG to that of the scrambler SRG. That is, in the DSS system the samples of the scrambler SRG sequence, which SRG sequence represents information on the scrambler SRG state, are generated, then transmitted to the descrambler, and the descrambler SRG state is corrected using the samples of the scrambler SRG sequence to become identical to the scrambler SRG state, while in the FSS system the SRGs in both the scrambler and the descrambler are synchronized by resetting the states of both SRGs to a prespecified state at the start of each frame.
In the DSS system of CCITT comprising a scrambler and a descrambler, the scrambler scrambles the scrambler input bitstream by adding the scrambler SRG sequence thereto, thereby generating a scrambled bitstream. Additionally, in the scrambler, samples of the scrambler SRG sequence are picked up at sampling times of uniform interval, then transmitted to the descrambler in parallel with the scrambled bitstream. On the other hand, receiving the scrambled bitstream and the samples of the scrambler SRG sequence, the descrambler corrects using the samples of the scrambler SRG sequence the descrambler SRG state to be identical to the scrambler SRG state. Thereafter, in the descrambler the transmitted scrambled bitstream is descrambled by adding the descrambler SRG sequence thereto, thereby obtaining descrambled bitstream. This descrambled bitstream is then identified to the original input bitstream of the scrambler by the descrambler. In result, the scrambled original bitstream can be descrambled by the descrambler.
However, the known DSS system only uses samples corresponding to sampling times of uniform interval, thus it is obliged to have a disadvantage in that it should have a complex construction resulting from a clock, storage and a complex correction circuitry, which are adapted to pick up and store such samples, furthermore, it has another disadvantage in that it can not use samples which are picked up at sampling times of non-uniform intervals.